Pipeline MD5 implementations on FPGA with data forwarding (リコンフィギャラブルシステム)

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概要

• 論文の詳細を見る

• The hash algorithm or message digest algorithm such as SHA and MD5 are used to generate a unique message digest for an arbitrary message. This paper describes 3 stages pipeline MD5 implementations on FPGA. This work removes the data dependency of a single step inside the main loop of the MD5 algorithm by data forwarding methodology, and breaks the computation into 3 pipeline stages. Two implementations without/with BRAM are given. They occupy 1010 and 885 hardware slices on Xilinx Vertex-II XC2V4000-6 FPGA chip, and achieve 700 Mbps and 746 Mbps, respectively.

• 社団法人電子情報通信学会の論文
• 2007-09-13

著者

• Hoang Anh

  Department Of Vlsi System Design Ritsumeikan University

• Oyanagi Shigeru

  Department Of Computer Science Ritsumeikan University

• YAMAZAKI Katsuhiro

  Department of VLSI System Design, College of Science and Engineering, Ritsumeikan University

• Oyanagi Shigeru

  Department Of Computer Science College Of Information Science And Engineering Ritsumeikan University

• Yamazaki Katsuhiro

  Department Of Vlsi System Design Ritsumeikan University

• Yamazaki Katsuhiro

  Department Of Computer Science Faculty Of Science And Engineering Ritsumeikan University

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