A New Breakdown Phenomenon in Fine Structured VLSI Circuits

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概要

• 論文の詳細を見る

• In fine structured n-channel MOS VLSI circuits, it is unavoidable that the n^+ diffusion layer for the power supply line (V_<DD>) is located near that for the ground line (V_<SS>). The breakdown voltage between V_<DD> and V_<SS> is reduced significantly by the substrate current generated in the surrounding MOSFET's. The resultant current flowing from V_<DD> to V_<SS> becomes large enough to cause various kinds of catastrophic destructions. This phenomenon is well explained by considering the effect of the increased substrate potential of the parasitic V_<SS>-substrate-V_<DD> bipolar transistor.

• 社団法人応用物理学会の論文
• 1981-07-05

著者

• MIYAMOTO Kazutoshi

  Mitsubishi Electric Corporation

• Miyamoto Kazutoshi

  Mitsubishi Electric Corporation Kitaitami Works

• Matsumoto Heihachi

  Mitsubishi Electric Co. Kitaitami Works

• Matsumoto Heihachi

  Mitsubishi Electric Corporation Kitaitami Works

• OHBAYASHI Yoshikazu

  Mitsubishi Electric Corporation, Kitaitami Works

• OHKURA Isao

  Mitsubishi Electric Corporation, Kitaitami Works

• MATSUMURA Hiroshi

  Mitsubishi Electric Corporation, Kitaitami Works

• Ohkura Isao

  Mitsubishi Electric Corporation Kitaitami Works

• Ohbayashi Yoshikazu

  Mitsubishi Electric Corporation Kitaitami Works

• Matsumura Hiroshi

  Mitsubishi Electric Corporation Kitaitami Works

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• The Effect of Temperature on Hot Electron Trapping in MOSFET's
• Time Dependent Dielectric Breakdown of Thin SiO_2 Films
• The Effect of Gate Bias on Hot Electron Trapping
• A New Breakdown Phenomenon in Fine Structured VLSI Circuits

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