CONCAVE-DMOSFET : A New Super-Low On-Resistance Power MOSFET

概要

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This paper describes a new super-low on-resistance power MOSFET. The new transistor "CONCAVE-DMOS-FET" has a concave channel structure fabricated not by trench etching technique, but by a combination of local oxidation of silicon (LOCOS) and diffusion self-alignment using oxide film as a double diffusion mask. The CON-CAVE-DMOSFET based on 16 μm cell design has been fabricated for the first time, and the specific on-resistance of 75 mΩ・mm^2 with breakdown voltage of 50 V has been achieved. This specific on-resistance is the lowest ever reported for power MOSFETs of comparable same design rule. The lowest value has been realized by means of the CONCAVE-MOS technology, which eliminates JFET resistance and provides a damage-free concave surface resulting in high channel mobility of 300 cm^2/V・s.
社団法人応用物理学会の論文
1995-02-28