Downsizing Gold Wires to Submicron Range: A Self-Planarized Au Metallization Process by Selective Electroplating for Si LSI Applications

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概要

• 論文の詳細を見る

• A self-planarized Au metallization process by electrolytic plating has been developed for metal interconnections in the submicron range. Gold wires with depth-to-width aspect ratio higher than 2 were fabricated in a buried structure within the dielectric spacer. By etching of Au and oxidizing the surface of TiW in the field, the gold wires can be selectively formed and planarized within the dielectrics. This process can provide desired properties of conductor structures for Si LSI applications. More important, the process is economically viable due to its simplicity and low cost in capital equipment purchase / maintenance and operation.

• 社団法人応用物理学会の論文
• 1995-07-15

著者

• Lo Tai-chin

  Department Of Electrical And Electronic Engineering Hong Kong University Of Science And Technology

• Lo Tai-chin

  Department Of Electrical And Electronic Engineering The Hong Kong University Of Science And Technolo

• Chan Miu-ying

  Department Of Electrical And Electronic Engineering The Hong Kong University Of Science And Technolo

関連論文

• Cross-Sectional Transmission Electron Microscopy Study of Si/SiGe Heterojunction Bipolar Transistor Structure Grown by Ultra-High Vacuum Chemical Vapor Deposition
• Reaction Mechanism of Selective Plating between TiW and Au:An Innovative Metallization Scheme for High-Speed Electronics
• Optimization of a Novel Self-Planarizing Au Metallization Process for Practical VLSI Applications
• Downsizing Gold Wires to Submicron Range: A Self-Planarized Au Metallization Process by Selective Electroplating for Si LSI Applications

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