Optimization of a Novel Self-Planarizing Au Metallization Process for Practical VLSI Applications

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概要

• 論文の詳細を見る

• A self-planarizing Au metallization process by selective electrolytic plating was developed for metal interconnections in the submicron range. Problems still remain concerning the simultaneously formation of a large wide gold pattern with submicron features. A 'trilevel-resist' filling process was developed in this work to overcome these problems. Moreover, optimization of the selective plating process was achieved. Thickness uniformity of plated gold wires with various dimensions can be maintained at better than 8.4% across 4-inch wafers.

• 社団法人応用物理学会の論文
• 1996-11-15

著者

• Lo Tai-chin

  Department Of Electrical And Electronic Engineering Hong Kong University Of Science And Technology

• Lo Tai-chin

  Department Of Electrical And Electronic Engineering The Hong Kong University Of Science And Technolo

• Chan M‐y

  Department Of Electrical And Electronic Engineering The Hong Kong University Of Science And Technolo

• CHAN Miu-Ying

  Department of Electrical and Electronic Engineering, The Hong Kong University of Science and Technol

• Chan Miu-ying

  Department Of Electrical And Electronic Engineering The Hong Kong University Of Science And Technolo

関連論文

• Cross-Sectional Transmission Electron Microscopy Study of Si/SiGe Heterojunction Bipolar Transistor Structure Grown by Ultra-High Vacuum Chemical Vapor Deposition
• Reaction Mechanism of Selective Plating between TiW and Au:An Innovative Metallization Scheme for High-Speed Electronics
• Optimization of a Novel Self-Planarizing Au Metallization Process for Practical VLSI Applications
• Downsizing Gold Wires to Submicron Range: A Self-Planarized Au Metallization Process by Selective Electroplating for Si LSI Applications

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