SOI (Silicon-On-Insulator) for High Speed Ultra Large Scale Integration

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概要

• 論文の詳細を見る

• Bulk complementary metal-oxide-semiconductor (CMOS) technology scaling can not sustain the historical rate of speed increase. A realistic target for silicon-on-insulator (SON) delay and power reductions in comparison to bulk technology are 40% and 30%, independent of scaling, mostly through capacitance reduction. Denser isolation allows more compact layout and easy integration of different high speed (E/D NMOS), low power (CMOS), analog (bipolar, grounded-body CMOS) and memory devices. Silicon device speed record (13 ps at 1.5 V, 300 K) has been set with SOI E/D NMOS. Leakage current due to steady state and transient floating-body induced threshold lowering (FITL) is a device issue which deserves more attention.

• 社団法人応用物理学会の論文
• 1994-01-30

著者

• Hu Chenming

  Department Of Electrical Engineering & Computer Sciences University Of California

• Hu Chenming

  Department Of Electrical Engineering And Computer Science University Of California

関連論文

• Impact of Gate Microstructure on Complementary Metal-Oxide-Semiconductor Transistor Performance
• New Method of Extracting Inversion Layer Thickness and Charge Profile and Its Impact on Scaled MOSFETs
• Hot-Carrier Reliability of 0.1μm Delta-Doped MOSFETs
• Deep-Trap Stress Induced Leakage Current Model for Nominal and Weak Oxides
• SOI (Silicon-On-Insulator) for High Speed Ultra Large Scale Integration

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