A 256Mb Synchronous Burst DDR SRAM using Single-crystal Silicon Thin Film Transistor(SSTFT) SRAM cell (ISSCC特集1 SRAM)
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概要
- 論文の詳細を見る
A 256Mb synchronous burst DDR SRAM is developed based on the 80nm SRAM technology with stacked single-crystal silicon thin film transistor SRAM cell. The chip is designed using hierarchical bit-line architecture.
- 2005-04-07
著者
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SUH Youngho
Memory Division, Samsung Electronics
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NAM Hyouyoun
Memory Division, Samsung Electronics
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AN Hungjun
Memory Division, Samsung Electronics
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KANG Sangbeom
Memory Division, Samsung Electronics
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Lim Hoon
Memory Division Samsung Electronics
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Byun Hyungeun
Memory Division Samsung Electronics
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Kang Sangbeom
Memory Division Samsung Electronics
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An Hungjun
Memory Division Samsung Electronics
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Suh Youngho
Memory Division Samsung Electronics
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Nam Hyouyoun
Memory Division Samsung Electronics
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Lee Youngdae
Memory Division Samsung Electronics
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Choi Byunggil
Memory Division Samsung Electronics
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Kwak Choongkeun
Memory Division Samsung Electronics
関連論文
- A 256Mb Synchronous Burst DDR SRAM using Single-crystal Silicon Thin Film Transistor(SSTFT) SRAM cell (ISSCC特集1 SRAM)
- A 256Mb Synchronous Burst DDR SRAM using Single-crystal Silicon Thin Film Transistor (SSTFT) SRAM cell
- Improved write methods for 64Mb Phase-change Random Access Memory(PRAM) (ISSCC特集3 不揮発性メモリ)
- Improved write methods for 64Mb Phase-change Random Access Memory (PRAM)