High-Performance VLSI Architecture for Separable Denominator 2-D State Space Digital Filters Based on Reduced-Dimensional Decomposition

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概要

• 論文の詳細を見る
• 社団法人電子情報通信学会の論文
• 2003-04-01

著者

• Tsunekawa Yoshitaka

  Faculty Of Engineering Iwate University

• TAYAMA Norio

  Faculty of Engineering, Iwate University

• NOZAKI Takeshi

  Faculty of Engineering,Iwate University

• Tayama Norio

  Faculty Of Engineering Iwate University

• Nozaki Takeshi

  Faculty Of Engineering Iwate University

関連論文

• High-Performance VLSI Architecture of the LMS Adaptive Filter Using 4-2 Adders
• Analysis of the Convergence Condition of LMS Adaptive Digital Filter Using Distributed Arithmetic
• High-Performance Multiprocessor Implementation for Block-State Realization of State-Space Digital Filters (Special Section of Papers Selected from JTC-CSCC'93)
• High-Performance VLSI Architecture for Separable Denominator 2-D State Space Digital Filters Based on Reduced-Dimensional Decomposition

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