Analysis of the Convergence Condition of LMS Adaptive Digital Filter Using Distributed Arithmetic
スポンサーリンク
概要
- 論文の詳細を見る
An LMS adaptive digital filter using distributed arithmetic (DA-ADF) has been proposed. Cowan and others proposed the DA adaptive algorithm with offset binary coding for the simple derivation of an algorithm and the use of an oddsymmetry property of adaptive function space (AFS) [3], [5], [10]. However, we indicated that a convergence speed of this DA adaptive algorithm degraded extremely by our computer simulations [6]. To overcome these problems, we have proposed the DA adaptive algorithm generalized with two's complement representation and effective architectures. Our DA-ADF has performances of a high speed, small output latency, a good convergence speed, small-scale hardware and lower power dissipation for higher order, simultaneously. In this paper, we analyze a convergence condition of DA adaptive algorithm that has never been considered theoretically [8], [9]. From this analysis, we indicate that the convergence speed is depended on a distribution of eigenvalues of an auto-correlation matrix of an extended input signal vector [8], [9]. Furthermore, we obtain the eigenvalues theoretically. As a result, we clearly show that our DA-ADF has an advantage of the conventional DA-ADF in the convergence speed.
- 社団法人電子情報通信学会の論文
- 2002-06-01
著者
-
Tsunekawa Y
Faculty Of Engineering Iwate University
-
Tsunekawa Yoshitaka
Faculty Of Engineering Iwate University
-
TAKAHASHI Kyo
Iwate Industrial Research Institute
-
Takahashi Kyo
Iwate Industrial Technology Junior College
-
TAYAMA Norio
Faculty of Engineering, Iwate University
-
SEKI Kyoushirou
Faculty of Engineering, Iwate University
-
Tayama Norio
Faculty Of Engineering Iwate University
-
Seki Kyoushirou
Faculty Of Engineering Iwate University
関連論文
- High-Performance VLSI Architecture of the LMS Adaptive Filter Using 4-2 Adders
- Analysis of the Convergence Condition of LMS Adaptive Digital Filter Using Distributed Arithmetic
- High-Performance Multiprocessor Implementation for Block-State Realization of State-Space Digital Filters (Special Section of Papers Selected from JTC-CSCC'93)
- High-Performance VLSI Architecture for Separable Denominator 2-D State Space Digital Filters Based on Reduced-Dimensional Decomposition