High-Performance Multiprocessor Implementation for Block-State Realization of State-Space Digital Filters (Special Section of Papers Selected from JTC-CSCC'93)

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概要

• 論文の詳細を見る

• This paper proposes high-performance multiprocessor implementation for real-time one-dimensional (1-D) statespace digital filters (SSDFs). The block-state realization of SSDFs (BSRDF) is suitable for their high speed realization and gives the characteristics of high accuracy. Previously we proposed a VLSI-oriented highly parallel architecture for BSRDF. For the purpose of speeding up and reducing hardware complexity, the distributed arithmetic, of which processing time depends only on word length, is applied to this architecture. It is implemented as a 2-D SIMD processor array, and the processor consists of n homogeneous processing elements (PEs), n being filter order. The high sampling rate of one or more hundred MHz becomes possible for high filter order. Moreover, the number of I/O data per processor can be a small fixed value for any filter order, and the number of gates can also be smaller than that in the case of using multiplier. Consequently, this proposed system can be implemented easily even in the present VLSI environment.

• 社団法人電子情報通信学会の論文
• 1994-06-25

著者

• Tsunekawa Yoshitaka

  Faculty Of Engineering Iwate University

• Seki Kyousiro

  Faculty of Engineering, Iwate University

• Seki Kyousiro

  Faculty Of Engineering Iwate University

関連論文

• High-Performance VLSI Architecture of the LMS Adaptive Filter Using 4-2 Adders
• Analysis of the Convergence Condition of LMS Adaptive Digital Filter Using Distributed Arithmetic
• High-Performance Multiprocessor Implementation for Block-State Realization of State-Space Digital Filters (Special Section of Papers Selected from JTC-CSCC'93)
• High-Performance VLSI Architecture for Separable Denominator 2-D State Space Digital Filters Based on Reduced-Dimensional Decomposition

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