New Test Structures for Evaluating the Scaling Limit of a Narrow U-Groove Isolation Structure (Special Issue on Microelectronic Test Structures)
スポンサーリンク
概要
- 論文の詳細を見る
New test structures for evaluating isolation capacitance (C_<TS>) and isolation breakdown voltage (BV_<CCO>) have been developed. Using these test structures, we examined the scaling limit of the width and the structure of narrow isolation U-grooves for high-speed and high-density LSIs. We separated the capacitance C_<TS> into two components, C_<TSS> (bottom component) and C_<TSL> (peripheral component), and analyzed the effect of the device structure (isolation width and filling materials) on C_<TS>. We found tha the minimum width of the isolation U-groove is especially limited by the increased isolation capacitance between the neighboring N^+ buried layers. The minimum width is about 0.31μm even when SiO_2 is used as a filling material. So we developed an effective method to overcome this limitation. Use of a double-trench structure and/or an SOI substrate meet the requirement. A double-trench structure can reduce C_<TS> by more than 50%, while SOI substrates gives reduced C_<TS>, high BV_<CCO>, high α-ray immunity, and reduced process steps.
- 一般社団法人電子情報通信学会の論文
- 1999-04-25
著者
-
Hashimoto Takashi
Device Development Center Hitachi Ltd.
-
TAMAKI Yoichi
Device Development Center, Hitachi Ltd.
-
Tamaki Yoichi
Device Development Center Hitachi Ltd.
関連論文
- A 1.5-ns Cycle-Time 18-kb Pseudo-Dual-Port RAM with 9K Logic Gates (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
- HCI-Free Selective Epitaxial SiGe Growth by LPCVD for 80-GHz BiCMOS Production
- Copper Wires for High Speed Logic LSI Prepared by Low Pressure Long Throw Sputtering Method
- New Test Structures for Evaluating the Scaling Limit of a Narrow U-Groove Isolation Structure (Special Issue on Microelectronic Test Structures)