4-2 Compressor with Complementary Pass-Transistor Logic

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概要

• 論文の詳細を見る

• This report describes 4-2 compressors composed of Complementary Pass-Transistor Logic (CPL). We will show that circuit designs of the 4-2 compressors can be optimized for high speed and small size using only exclusive-OR's and multiplexers. According to a circuit simulation with 0.8 μm CMOS device parameters, the maximum propagation delay and the average power consumption per unit adder are 1.32 ns and .6 pJ, respectively.

• 社団法人電子情報通信学会の論文
• 1994-04-25

著者

• Kubota Y

  Sharp Corporation

• Toyoyama Shinji

  Central Research Laboratories Sharp Corporation

• TSUCHIMOTO Shuhei

  Central Research Laboratories, SHARP Corporation

• Tsuchimoto S

  Central Research Laboratories Sharp Corporation

• Tsuchimoto Shuhei

  Central Research Laboratories Sharp Corporation

• Kanie Youji

  Central Research Laboratories, SHARP Corporation

• Kubota Yasushi

  Central Research Laboratories, SHARP Corporation

• Iwase Yasuaki

  Central Research Laboratories, SHARP Corporation

• Iwase Yasuaki

  Central Research Laboratories Sharp Corporation

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