A Phase Compensation Technique without Capacitors for the CMOS Circuit with a Very Low Impedance Terminal(Special Section on Analog Circuit Techniques and Related Topics)
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概要
- 論文の詳細を見る
A lower impedance terminal is necessary for an input terminal of current-mode circuits and an output terminal of voltage-mode circuits to reduce an error and distortion in analog signal processing.Thus, the CMOS circuit with a very low impedance terminal(VLIT circuit)is a useful analog building block to achieve the above purpose.The very low impedance terminal in the VLIT circuit is performed by a shunt-series feedback configuration.However, the feedback generates a problem of instability and / or oscillation at the same time.The problem can be removed by a phase compensation capacitor as known well, but the capacitor is not desirable for integrated circuits due to its large area.This paper proposes a new phase compensation technique for the VLIT circuit.The proposed technique dose not need any capacitors to obtain a sufficient phase margin, and instead gives us the appropriate transistor sizes(Width and length of the gate).As a result, the VLIT circuit has an enough phase margin and operates stably.
- 社団法人電子情報通信学会の論文
- 2000-02-25
著者
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Hyogo A
Tokyo Univ. Sci. Noda‐shi Jpn
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Hyogo Akira
Department Of Electrical Engineering Faculty Of Science And Technology Science University Of Tokyo
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Hyogo Akira
The Faculty Of Science And Technology Science University Of Tokyo
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Sekine K
Tokyo Univ. Sci. Noda‐shi Jpn
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Sekine Keitaro
Department Of Electrical Engineering Faculty Of Science And Technology Science University Of Tokyo
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Sekine Keitaro
The Faculty Of Science And Technology Science University Of Tokyo
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Ibaragi Eitake
The Department Of Electrical Engineering Science University Of Tokyo
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HYOGO Akira
the Department of Electrical Engineering, Science University of Tokyo
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SEKINE Keitaro
the Department of Electrical Engineering, Science University of Tokyo
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