A CMOS Analog Multiplier Free from Mobility Reduction and Body Effect (Special Section on Analog Circuit Techniques and Related Topics)
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概要
- 論文の詳細を見る
This paper proposes a novel CMOS analog multiplier. As its significant merit, it is free from mobility reduction and body effect. Thus, the proposed multiplier is expected to have good linearity, comparing with conventional multipliers. Four transistors operating in the linear region constitute the input cell of the multiplier. Their sources and backgates are connected to the ground to cancel the body effect. Their gates are fixed to the same bias voltage to remove the effect of the mobility reduction. Input signals are applied to the drains of the input cell transistors through modified nullors. The simulation results show that THD is less than 0.8% for 0.6 V_<p-p> input signal at 2.5-V supply voltage, and that the 3-dB bandwidth is up to about 13.3 MHz.
- 社団法人電子情報通信学会の論文
- 1999-02-25
著者
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Hyogo A
Tokyo Univ. Sci. Noda‐shi Jpn
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Hyogo Akira
Department Of Electrical Engineering Faculty Of Science And Technology Science University Of Tokyo
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Hyogo Akira
The Faculty Of Science And Technology Science University Of Tokyo
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Sekine K
Tokyo Univ. Sci. Noda‐shi Jpn
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Sekine Keitaro
Department Of Electrical Engineering Faculty Of Science And Technology Science University Of Tokyo
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Sekine Keitaro
The Faculty Of Science And Technology Science University Of Tokyo
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Ibaragi Eitake
The Department Of Electrical Engineering Science University Of Tokyo
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IBARAGI Eitake
Department of Electrical Engineering, Science University of Tokyo
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