Layout Abstraction and Technology Retargeting for Leaf Cells (Special Section on VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• The importance of technology retargeting for hard IPs is getting increased. However, recent advances in process technologies make layout reuse too complicated to be done by conventional compactors. As an efficient approach, this paper proposes a flexible layout abstraction model and a new layout synthesis algorithm. The synthesis algorithm provies a concurrent procedure of detailed wiring, compaction, and transistor layout generation by using a scan line to get better layout results than conventional compactors. We have applied this method to the technology retargeting of actual cell layouts and have achieved quite good results comparable to hand-crafted designs.

• 1998-12-25

著者

• Akino T

  Department Of Electronic System And Information Engineering School Of Biology-oriented Science And T

• KUNINOBU Shigeo

  Corporate Semiconductor Development Division, Matsushita Electric Industrial Co., Ltd.

• Fukui M

  Matsushita Electric Industrial Co. Ltd. Nagaokakyo‐shi Jpn

• FUKUI Masahiro

  Corporate Semiconductor Development Division, Matsushita Electric Industrial Co., Ltd.,

• SHINOMIYA Noriko

  Corporate Semiconductor Development Division, Matsushita Electric Industrial Co., Ltd.,

• SAIKA Syunji

  Corporate Semiconductor Development Division, Matsushita Electric Industrial Co., Ltd.,

• AKINO Toshiro

  the Department of Electronic System and Information Engineering, School of Biology-Oriented Science

• Saika Shunji

  Advanced Lsi Technology Development Center Corporate Semiconductor Development Division Matsushita E

• Kuninobu S

  Corporate Semiconductor Development Division Matsushita Electric Industrial Co. Ltd.

• Kuninobu Shigeo

  Corporate Semiconductor Development Division Matsushita Electric Industrial Co. Ltd.

• Shinomiya N

  Soka Univ. Hachioji‐shi Jpn

• Fukui Masahiro

  Corporate Semiconductor Development Division Matsushita Electric Industrial Co. Ltd.

関連論文

• Partial Scan Design Methods Based on n-Fold Line-Up Structures and the State Justification of Pure Load/Hold Flip-Flops(Special Issue on Test and Diagnosis of VLSI)
• Layout Abstraction and Technology Retargeting for Leaf Cells (Special Section on VLSI Design and CAD Algorithms)
• WSSA : A High Performance Simulated Annealing and Its Application to Transistor Placement (Special Section on VLSI Design and CAD Algorithms)
• A Two-Dimensional Transistor Placement Algorithm for Cell Synthesis and Its Application to Standard Cells (Special Section on VLSI Design and CAD Algorithms)
• A New Approach of Fractal-Analysis Based Module Clustering for VLSI Placement (Special Section on VLSI Design and CAD Algorithms)
• Design Optimization by Using Flexible Pipelined Modules (Special Section on VLSI Design and CAD Algorithms)

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