WSSA : A High Performance Simulated Annealing and Its Application to Transistor Placement (Special Section on VLSI Design and CAD Algorithms)

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概要

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• Another high performance simulated annealing is proposed which we call widely stepping simulated annealing(WSSA). It flies from a starting high temperature to a finishing low temperature staying at only twenty or so temperatures to approach thermal equilibriums. We survey the phase transition in simulated annealing process and estimate the major cost variation (dE_c) at the critical temperature. The WSSA uses a function (H(t)) that represents the probability for a hill-climbing with the dE_c of cost increase to be accepted in Metropolis' Monte Carlo simulation at temperature t. We have applied the first version of WSSA to one dimensional transistor placement optimizations for several industrial standard cells, and compared its performance with simulated annealing with a geometrically scheduled cooling. The solutions by the WSSA are as good as, and sometimes much better than, the solutions by the simulated annealing, while the time consumption by the WSSA is properly under one 30th of that by the simulated annealing.

• 社団法人電子情報通信学会の論文
• 2000-12-25

著者

• Akino T

  Department Of Electronic System And Information Engineering School Of Biology-oriented Science And T

• Fukui M

  Matsushita Electric Industrial Co. Ltd. Nagaokakyo‐shi Jpn

• SAIKA Shunji

  Advanced LSI Technology Development Center, Corporate Semiconductor Development Division, Matsushita

• FUKUI Masahiro

  Advanced LSI Technology Development Center, Corporate Semiconductor Development Division, Matsushita

• TOYONAGA Masahiko

  Advanced LSI Technology Development Center, Corporate Semiconductor Development Division, Matsushita

• AKINO Toshiro

  Department of Electronic System and Information Engineering, School of Biology-Oriented Science and

• Toyonaga Masahiko

  Advanced Lsi Technology Development Center Corporate Semiconductor Development Division Matsushita E

• Saika Shunji

  Advanced Lsi Technology Development Center Corporate Semiconductor Development Division Matsushita E

関連論文

• Layout Abstraction and Technology Retargeting for Leaf Cells (Special Section on VLSI Design and CAD Algorithms)
• WSSA : A High Performance Simulated Annealing and Its Application to Transistor Placement (Special Section on VLSI Design and CAD Algorithms)
• A Two-Dimensional Transistor Placement Algorithm for Cell Synthesis and Its Application to Standard Cells (Special Section on VLSI Design and CAD Algorithms)
• A New Approach of Fractal-Analysis Based Module Clustering for VLSI Placement (Special Section on VLSI Design and CAD Algorithms)

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