A Two-Dimensional Transistor Placement Algorithm for Cell Synthesis and Its Application to Standard Cells (Special Section on VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• We propose a transistor placement algorithm to generate standard cell layout in a two-dimensional placement style. The algorithm optimizes the one-dimensional placement in the first stage, folds the large transistors in the second stage, and optimizes the two-dimensional placement in the final stage. We also propose "cost function" based on wiring length, which closely match the cell optimization. This transistor placement algorithm has been applied to several standard cells, and demonstrated the capability to generate a two-dimensional placement that is comparable to manually designed placement.

• 社団法人電子情報通信学会の論文
• 1997-10-25

著者

• Akino T

  Department Of Electronic System And Information Engineering School Of Biology-oriented Science And T

• Fukui M

  Matsushita Electric Industrial Co. Ltd. Nagaokakyo‐shi Jpn

• SAIKA Shunji

  Advanced LSI Technology Development Center, Corporate Semiconductor Development Division, Matsushita

• FUKUI Masahiro

  Advanced LSI Technology Development Center, Corporate Semiconductor Development Division, Matsushita

• SHINOMIYA Noriko

  Corporate Semiconductor Development Division, Matsushita Electric Industrial Co., Ltd.,

• AKINO Toshiro

  the Department of Electronic System and Information Engineering, School of Biology-Oriented Science

• SHINOMIYA Noriko

  Advanced LSI Technology Development Center, Matsushita Electric Industrial Co., Ltd.

• KUNINOBU Shigeo

  Microprocessor Development Center, Matsushita Electric Industrial Co., Ltd.

• Saika Shunji

  Advanced Lsi Technology Development Center Corporate Semiconductor Development Division Matsushita E

• Kuninobu S

  Corporate Semiconductor Development Division Matsushita Electric Industrial Co. Ltd.

• Shinomiya N

  Soka Univ. Hachioji‐shi Jpn

関連論文

• Layout Abstraction and Technology Retargeting for Leaf Cells (Special Section on VLSI Design and CAD Algorithms)
• WSSA : A High Performance Simulated Annealing and Its Application to Transistor Placement (Special Section on VLSI Design and CAD Algorithms)
• A Two-Dimensional Transistor Placement Algorithm for Cell Synthesis and Its Application to Standard Cells (Special Section on VLSI Design and CAD Algorithms)
• A New Approach of Fractal-Analysis Based Module Clustering for VLSI Placement (Special Section on VLSI Design and CAD Algorithms)

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