An Adder-Free Method for a Small Size π/4 Shift QPSK Signal Generator (Special Section on Analog Circuit Techniques for System-on-Chip Integration)

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概要

• 論文の詳細を見る

• A novel adder-free architecture for realizing a small-size π/4-shift QPSK signal generator IC is presented. In order to realize an adder function, analog current-mode addition is utilized instead of digital adders. Impulse responses of a roll-off filter are stored in a ROM as a Δ-Σ modulated one-bit data stream. This can greatly reduce the die size to 0.8 mm x 0.8 mm while maintaining high modulation accuracy. The test chip was fabricated by using the standard 0.8μm CMOS technology, and the chip achieved 1.8% vector modulation error with a 2.7 V power supply.

• 社団法人電子情報通信学会の論文
• 1997-02-25

著者

• TANIMOTO Hiroshi

  Research and Development Center, Toshiba Corporation

• TAKAHASHI Chikau

  Toshiba R amp D Center

• Koizumi Masayuki

  Toshiba Semiconductor Division Ii Toshiba Corporation

• Koizumi Masayuki

  Toshiba Corporation Semiconductor Company

• Koizumi Masayuki

  Niigata Institute Of Technology

• Yasuda A

  Toshiba Corp. Kawasaki‐shi Jpn

• YASUDA Akira

  Research and Development Center, TOSHIBA CORPORATION

• YAMAGUCHI Akira

  Toshiba Semiconductor Division II, TOSHIBA CORPORATION

• Takahashi Chikau

  Toshiba Semiconductor System Engineering Center Toshiba Corporation

• Tanimoto Hiroshi

  Research And Development Center Toshiba Corporation

• Yasuda Akira

  Research And Development Center Toshiba Corporation

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