A High Speed Fuzzy Inference Processor with Dynamic Analysis and Scheduling Capabilities(Computer Components)

スポンサーリンク

概要

• 論文の詳細を見る

• The most obvious architectural solution for high-speed fuzzy inference is to exploit temporal parallelism and spatial parallelism inherited in a fuzzy inference execution. However, in fact, the active rules in each fuzzy inference execution are often only a small part of the total rules. In this paper, we present a new architecture that uses less hardware resources by discarding non-active rules in the earlier pipeline stage. Compared with previous work, implementation data show that the proposed architecture achieves very good results in terms of the inference speed and the chip area.

• 社団法人電子情報通信学会の論文
• 2005-10-01

著者

• HUANG Shih-Hsu

  Department of Electronic Engineering, Chung Yuan Christian University

• Huang Shih‐hsu

  Chung Yuan Christian Univ. Chung Li Twn

• Huang Shih-hsu

  Department Of Electronic Engineering Chung Yuan Christian University

• LAI Jian-Yuan

  Department of Electronic Engineering, Chung Yuan Christian University

• Lai Jian-yuan

  Department Of Electronic Engineering Chung Yuan Christian University

関連論文

• Opposite-Phase Clock Tree for Peak Current Reduction(Circuit Synthesis,VLSI Design and CAD Algorithms)
• A High Speed Fuzzy Inference Processor with Dynamic Analysis and Scheduling Capabilities(Computer Components)
• An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management
• An ILP Approach to the Slack Driven Scheduling Problem(VLSI Design Technology and CAD)
• A Timing Driven Crosstalk Optimizer for Gridded Channel Routing(Computer Components)
• An ILP approach to surge current minimization in high-level synthesis
• Temperature-Aware Layer Assignment for Three-Dimensional Integrated Circuits

スポンサーリンク