A Timing Driven Crosstalk Optimizer for Gridded Channel Routing(Computer Components)

スポンサーリンク

概要

• 論文の詳細を見る

• The relative window method provides quantitative crosstalk delay degradation for the post-layout timing analysis in deep submicron VLSI design. However, to the best of our knowledge, the relative window method has not been applied to the crosstalk minimization in gridded channel routing problem. Most conventional crosstalk optimizers only use the coupling length to estimate the crosstalk. In this paper, we present a post-layout timing driven crosstalk optimizer based on the relative window method. According to the relative signal arrival time and the coupling length, we define a delay degradation graph to describe the crosstalks between nets in a routing solution. Our optimization goal is to maximize the time slack by iteratively improving the delay degradation graph without increasing the channel height. Benchmark data consistently show that our post-layout timing driven crosstalk optimizer can further improve the routing solution obtained by a conventional crosstalk optimizer.

• 社団法人電子情報通信学会の論文
• 2004-06-01

著者

• Huang Shih-hsu

  Department Of Electronic Engineering Chung Yuan Christian University

• HSU Yi-Siang

  Department of Electronic Engineering, Chung Yuan Christian University

• LIN Chiu-Cheng

  Department of Electronic Engineering, Chung Yuan Christian University

• Hsu Yi-siang

  Department Of Electronic Engineering Chung Yuan Christian University

• Lin Chiu-cheng

  Department Of Electronic Engineering Chung Yuan Christian University

関連論文

• Opposite-Phase Clock Tree for Peak Current Reduction(Circuit Synthesis,VLSI Design and CAD Algorithms)
• A High Speed Fuzzy Inference Processor with Dynamic Analysis and Scheduling Capabilities(Computer Components)
• An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management
• An ILP Approach to the Slack Driven Scheduling Problem(VLSI Design Technology and CAD)
• A Timing Driven Crosstalk Optimizer for Gridded Channel Routing(Computer Components)
• An ILP approach to surge current minimization in high-level synthesis
• Temperature-Aware Layer Assignment for Three-Dimensional Integrated Circuits

スポンサーリンク