Opposite-Phase Clock Tree for Peak Current Reduction(Circuit Synthesis,<Special Section>VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• Although much research effort has been devoted to the minimization of total power consumption caused by the clock tree, no attention has been paid to the minimization of the peak current caused by it. In this paper, we propose an opposite-phase clock scheme to reduce the peak current incurred by the clock tree. Our basic idea is to balance the charging and discharging activities. According to the output operation, the clock buffers that transit simultaneously are divided into two groups: half of the clock buffers transit at the same phase of the clock source, while the other half transit at the opposite phase of the clock source. As a consequence, the opposite-phase clock scheme significantly reduces the peak current caused by the clock tree. Experimental data show that our approach can be applied at different design stages in the existing design flow.

• 社団法人電子情報通信学会の論文
• 2007-12-01

著者

• Nieh Yow-tyng

  Department Of Electronic Engineering Chung Yuan Christian University

• HUANG Shih-Hsu

  Department of Electronic Engineering, Chung Yuan Christian University

• HSU Sheng-Yu

  SoC Technology Center, Industrial Technology Research Institute

• Huang Shih-hsu

  Department Of Electronic Engineering Chung Yuan Christian University

• Hsu Sheng-yu

  Soc Technology Center Industrial Technology Research Institute

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