VLSI Implementation of Lifting Discrete Wavelet Transform Using the 5/3 Filter(Regular Section)

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概要

• 論文の詳細を見る

• In this paper, a VLSI architecture for lifting-based discrete wavelet transform (LDWT) is presented. Our architecture folds the computations of all resolution levels into the same low-pass and high-pass units to achieve higher hardware utilization. Due to the regular and flexible structure of the design, its area is independent of the length of the 1-D input sequence, and its latency is independent of the number of resolution levels. For the computations of analysis process of N-sample 1-D 3-level LDWT, our design takes about N clock cycles and requires 2 multipliers, 4 adders, and 22 registers. It is fabricated with TSMG 0.35-μm cell library and has a die size of 1.2 × 1.2 mm^2. The power dissipation of the chip is about 0.4 W at the clock rate of 80MHz.

• 一般社団法人電子情報通信学会の論文
• 2002-12-01

著者

• Chen Pei-yin

  Department Of Computer Science And Information Engineering National Cheng Kung University

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• VLSI Implementation of Lifting Discrete Wavelet Transform Using the 5/3 Filter(Regular Section)

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