VLSI Architecture for 2-D 3-Level Lifting-Based Discrete Wavelet Transform (VLSI Design Technology and CAD)

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概要

• 論文の詳細を見る

• Discrete wavelet transform has been successfully used in many image processing applications. In this paper, we present an efficient VLSf architecture for 2-D 3-level lifting-based discrete wavelet transform using the (5, 3) filter. All three-level coefficients are computed interlacingly and periodically to achieve higher hardware utilization and better throughput. In comparison with other VLSI architectures, our architecture requires less size of storage and faster computation speed.

• 社団法人電子情報通信学会の論文
• 2004-01-01

著者

• Chen P‐y

  Department Of Electronic Engineering Southern Taiwan University Of Technology

• Chen Pei-yin

  Department Of Computer Science And Information Engineering National Cheng Kung University

関連論文

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• A Low-Cost CAVLC Encoder(Electronic Circuits)
• VLSI Architecture for 2-D 3-Level Lifting-Based Discrete Wavelet Transform (VLSI Design Technology and CAD)
• VLSI Implementation of Lifting Discrete Wavelet Transform Using the 5/3 Filter(Regular Section)

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