An Efficient VLSI Architecture of 1-D Lifting Discrete Wavelet Transform(Integrated Electronics)

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概要

• 論文の詳細を見る

• An efficient VLSI architecture for 1-D lifting DWT is proposed in this paper. To achieve higherhardware utilization and higher throughput, the computations of all resolution levels are folded to both the same high-pass and low-pass filters. Besides, the number of registers in the folded architecture is minimized by using the generalized lifetime analysis. Owing to its regular and flexible structure, the design can be extended easily into different resolution levels, and its area is independent of the length of the 1-D input sequence. Compared with other known architectures, our design requires the least computing time for 1-D lifting DWT.

• 社団法人電子情報通信学会の論文
• 2004-11-01

著者

• Chen Pei-yin

  Department Of Computer Science And Information Engineering National Cheng Kung University

• CHEN Shung-Chih

  Department of Electronic Engineering, Southern Taiwan University of Technology

• Chen Shung-chih

  Department Of Electronic Engineering Southern Taiwan University Of Technology

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