Evaluation of Delay Testing Based on Path Selection(Timing Verifivation and Test Generation)(<Special Section>VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• Since a logic circuit often has too many paths to test delay of all paths, it is necessary for path delay testing to limit the number of paths to be tested. The paths to be tested should have large delay because such paths more likely cause a fault. Additionally, a test set for the paths are required to detect other models of faults as many as possible. In this paper, we investigate two typical criteria of path selection for path delay testing. From our experiments, we observe that test patterns for the longest paths cannot cover many local delay defects such as transition faults.

• 社団法人電子情報通信学会の論文
• 2003-12-01

著者

• Kajihara Seiji

  Graduate School Of Computer Science And Systems Engineering Kyushu Institute Of Technology:center Fo

• Takeoka Sadami

  Semiconductor Company Matsushita Electric Industrial Co. Ltd.

• FUKUNAGA Masayasu

  Graduate School of Computer Science and Systems Engineering, Kyushu Institute of Technology

• YOSHIMURA Shinichi

  Semiconductor Company, Matsushita Electric Industrial Co., Ltd.

• Fukunaga Masayasu

  Graduate School Of Computer Science And Systems Engineering Kyushu Institute Of Technology

• Yoshimura Shinichi

  Semiconductor Company Matsushita Electric Industrial Co. Ltd.

関連論文

• A Partial Scan Design Approach based on Register-Transfer Level Testability Analysis (Special Issue on Synthesis and Verification of Hardware Design)
• On Statistical Estimation of Fault Efficiency for Path Delay Faults Based on Untestable Path Analysis(Dependable Computing)
• Evaluation of Delay Testing Based on Path Selection(Timing Verifivation and Test Generation)(VLSI Design and CAD Algorithms)
• Average Power Reduction in Scan Testing by Test Vector Modification(Special Issue on Test and Verification of VLSI)

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