Average Power Reduction in Scan Testing by Test Vector Modification(Special Issue on Test and Verification of VLSI)

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概要

• 論文の詳細を見る

• This paper presents a test vector modification method for reducing average power dissipation during test application for a full-scan circuit. The method first identifies a set of don't care (X) inputs of given test vectors, to which either logic value 0 or 1 can be assigned without losing fault coverage. Then, the method reassigns logic values to the X inputs so as to decrease switching activity of the circuit during scan shifting. Experimental results for benchmark circuits show the proposed method could decrease switching activity of a given test set to 45% of the original test sets in average.

• 社団法人電子情報通信学会の論文
• 2002-10-01

著者

• Miyase Kohei

  Graduate School Of Computer Science And Systems Engineering Kyushu Institute Of Technology

• Kajihara Seiji

  Graduate School Of Computer Science And Systems Engineering Kyushu Institute Of Technology:center Fo

• ISHIDA Koji

  Graduate School of Computer Science and Systems Engineering, Kyushu Institute of Technology

• Ishida Koji

  Graduate School Of Computer Science And Systems Engineering Kyushu Institute Of Technology

関連論文

• Evaluation of Delay Testing Based on Path Selection(Timing Verifivation and Test Generation)(VLSI Design and CAD Algorithms)
• Average Power Reduction in Scan Testing by Test Vector Modification(Special Issue on Test and Verification of VLSI)

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