A 350MHz 5.6GOPS / 1.4GFLOPS 4-Way VLIW Embedded Microprocessor (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)

概要

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A 5.6GOPS/1.4GFLOPS 350MHz, four-way very long instruction word (VLIW) microprocessor is developed for embedded applications in a 0.18μm five-layer-metal CMOS process. This processor features a two-way integer pipeline and two-way floating/media pipelines. Each floating pipeline and media pipeline has two-parallel and four-parallel single instruction multiple-data(SIMD) mechanisms, respectively. The processor has separate instruction and data caches, each of 16KB in size and having four-way set associative. The data cache employs a non-blocking technique and can process two load instructions in parallel. The processor had about a 50% clock net power reduction compared with one without power optimization. 6.7million transistors are integrated in an area of 7.5mm×7.5mm. Since all circuit blocks were developed using logic synthesis, the processor is easy to adapt to system-on-a-chip (SoC) applications.
社団法人電子情報通信学会の論文
2001-02-01