A 3.2 GFLOPS Neural Network Accelerator (Special Issue on New Concept Device and Novel Architecture LSIs)
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概要
- 論文の詳細を見る
We have developed a SIMD-type neural-network processor (NEURO4) and its software environment. With the SIMD architecture, the chip executes 24 operations in a clock cycle and achieves 1.2 GFLOPS peak performance. An accelerator board, which contains four NEURO4 chips, achieves 3.2 GFLOPS. In this paper we describe features of the neural network chip, accelerator board, software environment and performance evaluation for several neural network models (LVQ, BP and Hopfield). The 3.2 GFLOPS neural network accelerator board demonstrates 1.7 GCPS and 261 MCUPS for Hopfield networks.
- 社団法人電子情報通信学会の論文
- 1997-07-25
著者
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Tanaka Ken-ichi
Department Of Brain Science Okayama University Graduate School Of Medicine And Dentistry
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Kyuma Kazuo
Department Of Neural Amp Parallel Processing Technology Advanced Technology Rampd Center Mitsubishi
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Arima Yutaka
Department Of Neural Amp Parallel Processing Technology Advanced Technology Rampd Center Mitsubishi
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Komori Shinji
Department Of Neural Amp Parallel Processing Technology Advanced Technology Rampd Center Mitsubishi
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Kondo Yoshikazu
Department Of Neural Amp Parallel Processing Technology Advanced Technology Rampd Center Mitsubishi
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TSUBOTA Hirono
Department of Neural amp Parallel Processing Technology, Advanced Technology RampD Center, Mitsubish
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Tsubota Hirono
Department Of Neural Amp Parallel Processing Technology Advanced Technology Rampd Center Mitsubishi
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Tanaka Ken-ichi
Department Of Biophysics Faculty Of Science Kyoto University
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Tanaka Ken-ichi
Department Of Neural Amp Parallel Processing Technology Advanced Technology Rampd Center Mitsubishi
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