The RDT Router Chip: A Versatile Router for Supporting a Distributed Shared Memory

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概要

• 論文の詳細を見る

• JUMP-1 is currently under development by seven Japanese universities to establish techniques for building an efficient distributed shared memory on a massively parallel processor. It provides a coherent cache with reduced hierarchical bit-map directory scheme to achieve cost effective and high performance management. Messages for coherent cache are transferred through a fat tree on the RDT (Recursive Diagonal Torus) interconnection network. RDT router supports versatile functions including multicast and acknowledge combining for the reduced hierarchical bit-map directory scheme. By using 0.5 μm BiCMOS SOG technology, it can transfer all packets synchronized with a unique CPU clock (50 MHz). Long coaxial cables (4 m at maximum) are directly driven with the ECL interface of this chip. Using the dual port RAM, packet buffers allow to push and pull a flit of the packet simultaneously.

• 社団法人電子情報通信学会の論文
• 1997-09-25

著者

• Amano H

  Keio Univ. Yokohama‐shi Jpn

• Amano Hideharu

  Amano Laboratory Department Of Computer Science Keio University

• AMANO Hideharu

  the Department of Information and Computer Science, Keio University

• Kudoh T

  National Institute Of Advanced Industrial Science And Technology (aist)

• NISHI Hiroaki

  the Department of Computer Science, Keio University

• ANJO Ken-ichiro

  the Department of Computer Science, Keio University

• KUDOH Tomohiro

  the Department of Information Technology, Tokyo Engineering University

• Nishi H

  Starc (semiconductor Technol. Academic Res. Center) Yokohama‐shi Jpn

• Anjo Ken-ichiro

  The Department Of Computer Science Keio University

• Amano Hideharu

  The Department Of Computer Science Keio University

関連論文

• A Routing Algorithm for Multihop WDM Ring
• Wavelength Division Multiple Access Ring : Virtual Topology on a Simple Ring Network
• Message Transfer Algorithms on the Recursive Diagonal Torus
• MMLRU Selection Function : A Simple and Efficient Output Selection Function in Adaptive Routing(Computer Systems)
• A High-Speed, Highly-Reliable Network Switch for Parallel Computing System Using Optical Interconnection(Special Issue on Optical Interconnects/Optical Signal Processing)
• Architecture and Evaluation of a Third-Generation RHiNET Switch for High-Performance Parallel Computing( Development of Advanced Computer Systems)
• The RDT Router Chip: A Versatile Router for Supporting a Distributed Shared Memory
• An FPGA-Based Acceleration Method for Metabolic Simulation(Recornfigurable Systems)(Reconfigurable Systems)
• MINC: Multistage Interconnection Network with Cache Control Mechanism

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