A Proposition on Floating Gate Neuron MOS Macromodeling for Device Fabrications (Special Section on VLSI Design and CAD Algorithms)

概要

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A neuron MOS transistor has a floating gate and multiple input gates which are capacitively coupling with the floating gate. Dramatic reduction in the number of transistors and interconnections was achieved by employing the neuron MOS in circuit designs. Since the neuron MOS gate electrode is electrically floating, it is not necessarily easy to calculate the floating gate potential using circuit simulator SPICE. In order to simulate floating gate neuron MOS circuits, a macromodel which calculates the floating gate potential combining resistances and dependent voltage and current sources has been proposed. Eight kinds of neuron MOS circuits were designed and fabricated by a double polysilicon two level metal 1.2 μm CMOS process. Utilizing SPICE, all the neuron MOS circuits were confirmed to operate correctly. The apparent threshold voltage as seen from the input gate in the 2-input n-channel neuron MOS transistor is arbitrarily changed by a control gate signal. Multi-input neuron MOS inverters and neuron MOS full adder circuits have been successfully simulated. Moreover, the effectiveness of the proposed macromodel has been experimentally verified by fabricated circuit measurements. Measured results confirmed that 3-input neuron MOS inverter outputs the low level when the number of input gates to which a high level is applied is more than half of all input gates.
社団法人電子情報通信学会の論文
1999-11-25