A Fundamental Analysis of Single Event Effects on Clocked CVSL Circuits with Gated Feedback
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概要
- 論文の詳細を見る
Clocked cascade voltage switch logic (C2VSL) circuits with gated feedback were newly designed for synchronous systems. In order to investigate single event transient (SET) effects on the C2VSL circuits, SET effects on C2VSL EX-OR circuits were analyzed using SPICE. Simulation results have indicated that the C2VSL have increased tolerance to SET.
- 2011-06-01
著者
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Hatano Hiroshi
Department Of Applied Physics Osaka University
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Hatano Hiroshi
Department Of Electrical And Electronic Engineering Faculty Of Science And Technology Shizuoka Insti
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