Cell optimization for low power CM0S LSI

概要

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Recently, it is becoming important that ASICs with low power consumption are designed for specific products. In this trend, we tried to accomplish this target by scans of the design system. Generally speaking, it is natural that we should lower supply voltage to reduce total power consumption. However, this approach greatly depends on semi conductor process technology. We can not simply lower voltage at operation. But if power reduction is possible by the capability of design system it self, it becomes very effective. Then, we present a new method which is called Cell Optimizer to reduce LSI power consumption. Cell Optimizer is a function to determine what cell with same function should be adopted to reduce total LSI power in pre-physical design phase. Por.example, the three cells shown in Figure 1are defined as INVERTER. When we choos'e an inverter gate for our specific ASIC design, we must decide which cell is best for our requirement such as performance or total power.
一般社団法人情報処理学会の論文
1992-09-28