RTD/HEMT Logic Circuits and Their Functional Circuits Application
スポンサーリンク
概要
著者
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Nakashi Kenichi
Grad.school Of Information Sci.and Electrical Eng. Kyushu Univ.
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Nakashi Kenichi
Dept.of Electronic Device Eng. Grad.school Of Information Sci.and Electrical Eng. Kyushu Univ.
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TAKI Hideo
Dept.of Electrical Eng.,Faculty of Eng.,Kyushu Univ.
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KUDOU Yousuke
Dept.of Electrical Eng.,Faculty of Eng.,Kyushu Univ.
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Taki Hideo
Dept.of Electrical Eng. Faculty Of Eng. Kyushu Univ.
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Kudou Yousuke
Dept.of Electrical Eng. Faculty Of Eng. Kyushu Univ.
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KUDOU Yousuke[et
Dept.of Electrical Eng.,Faculty of Eng.,Kyushu Univ.
関連論文
- A Low Power 622MHz CMOS Phase-Locked Loop with Source Coupled VCO and Dynamic PFD (Special Section of Papers Selected from ITC-CSCC'96)
- A Phase Frequency Detector Constructed with Dynamic CMOS Gates for Low Power PLL
- Computer Simulation of Jitter Characteristics of PLL for Arbitrary Data and Jitter Patterns (Special Section of Papers Selected from JTC-CSCC'93)
- A Design of First-Order Delay-Line DPLL in 1.2μm CMOS Technology
- RTD/HEMT Logic Circuits and Their Functional Circuits Application