A Design of First-Order Delay-Line DPLL in 1.2μm CMOS Technology

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A Low Power 622MHz CMOS Phase-Locked Loop with Source Coupled VCO and Dynamic PFD (Special Section of Papers Selected from ITC-CSCC'96)
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Computer Simulation of Jitter Characteristics of PLL for Arbitrary Data and Jitter Patterns (Special Section of Papers Selected from JTC-CSCC'93)
A Design of First-Order Delay-Line DPLL in 1.2μm CMOS Technology
RTD/HEMT Logic Circuits and Their Functional Circuits Application

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