Design of High-Performance CMOS Level Converters Considering PVT Variations

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概要

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• CMOS SoCs can reduce power consumption while maintaining performance by adopting voltage scaling (VS) technologies. The operating speed of the level converter (LC) strongly affects the effectiveness of VS technologies. However, PVT variations can cause serious problems to the LC, because the state-of-the-art LC designs do not give enough attention to this issue. In this work, we proposed to analyze the impact of PVT variations on the performance of the LC using a previously developed heuristic sizing methodology. Based on the evaluation results from different operating corners with different offset voltages and temperatures, we proposed a variation-tolerant LC that achieves both high performance and low energy with a high tolerability for PVT variations.

• 2011-05-01

著者

• Chang Yu-juey

  Chung-cheng University

• Yeh Chingwei

  The Dept. Of Electrical Engineering Chung-cheng University

• Wang Jinn-shyan

  The Dept. Of Electrical Engineering Chung-cheng University

• Wang Jinn-shyan

  Dept. Of Electrical Engineering Chung-cheng University

• Yeh Chingwei

  Dept. Of Electrical Engineering Chung-cheng University

関連論文

• Heuristic Sizing Methodology for Designing High-Performance CMOS Level Converters with Balanced Rise and Fall Delays
• Design of High-Performance CMOS Level Converters Considering PVT Variations
• Design of 65 nm Sub-Threshold SRAM Using the Bitline Leakage Prediction Scheme and the Non-trimmed Sense Amplifier

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