Design of 65 nm Sub-Threshold SRAM Using the Bitline Leakage Prediction Scheme and the Non-trimmed Sense Amplifier

スポンサーリンク

概要

• 論文の詳細を見る
• 2012-01-01

著者

• Wang Jinn-shyan

  Dept. Of Electrical Engineering Chung-cheng University

• Lin Chi-chang

  Chung-cheng University

• CHANG Pei-Yao

  Dept. of Electrical Engineering, Chung-Cheng University

• Chang Pei-yao

  Dept. Of Electrical Engineering Chung-cheng University

関連論文

• Design of High-Performance CMOS Level Converters Considering PVT Variations
• Design of 65 nm Sub-Threshold SRAM Using the Bitline Leakage Prediction Scheme and the Non-trimmed Sense Amplifier

スポンサーリンク