Fixed-Width Group CSD Multiplier Design

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概要

• 論文の詳細を見る

• This paper presents an error compensation method for fixed-width group canonic signed digit (GCSD) multipliers that receive a W-bit input and generate a W-bit product. To efficiently compensate for the truncation error, the encoded signals from the GCSD multiplier are used for the generation of the error compensation bias. By Synopsys simulations, it is shown that the proposed method leads to up to 84% reduction in power consumption and up to 78% reduction in area compared with the fixed-width modified Booth multipliers.

• （社）電子情報通信学会の論文
• 2010-06-01

著者

• Cho Kyung‐ju

  Korea Assoc. Of Aids To Navigation (kaan) Seoul Kor

• Chung Jin‐gyun

  Chonbuk National Univ. Jeonju Kor

• CHO Kyung-Ju

  Korea Association of Aids to Navigation (KAAN)

• CHUNG Jin-Gyun

  Division of Electronics & Information Engr., Chonbuk National University

• Kim Yong-eun

  Division Of Electronics & Information Engr. Chonbuk National University

• Huang Xinming

  Dept. Of Electrical & Computer Engr. Worcester Polytechnic Institute

• KIM Yong-Eun

  Vehicle-IT Fusion Research Center, Korea Automotive Technology Institute

• HUANG Xinming

  Dep. of Electrical & Computer Engr., Worcester Polytechnic Institute

• Chung Jin-Gyun

  Division of Electronic Engineering, Chonbuk National University

関連論文

• CSD-Based Programmable Multiplier Design for Predetermined Coefficient Groups
• Low Power Small Area Modified Booth Multiplier Design for Predetermined Coefficients(VLSI Design Technology and CAD)
• Fixed-Width Group CSD Multiplier Design
• Memory Size Reduction Technique of SDF IFFT Architecture for OFDM-Based Applications
• Memory efficient IFFT design for OFDM-based applications

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