Memory Size Reduction Technique of SDF IFFT Architecture for OFDM-Based Applications

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概要

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• In this paper, to reduce the memory size requirements of IFFT for OFDM-based applications, we propose a new IFFT design technique based on a combined integer mapping of three IFFT input signals: modulated data, pilot and null signals. The proposed method focuses on reducing the size of memory cells in the first two stages of the single-path delay feedback (SDF) IFFT architectures since the first two stages require 75% of the total memory cells. By simulations of 2048-point IFFT design for cognitive radio systems, it is shown that the proposed IFFT design method achieves more than 13% reduction in gate count and 11% reduction in power consumption compared with conventional IFFT design.

著者

• CHUNG Jin-Gyun

  Division of Electronics & Information Engr., Chonbuk National University

• KIM Yong-Eun

  Korea Automotive Technology Institute (KATECH)

• JANG In-Gul

  Division of Electronic Engineering, IT Convergence Research Center, Chonbuk National University

• CHO Kyung-Ju

  Division of Electronic & Control Engineering, Wonkwang University

• CHUNG Jin-Gyun

  Division of Electronic Engineering, IT Convergence Research Center, Chonbuk National University

• Chung Jin-Gyun

  Division of Electronic Engineering, Chonbuk National University

関連論文

• CSD-Based Programmable Multiplier Design for Predetermined Coefficient Groups
• Fixed-Width Group CSD Multiplier Design
• Memory Size Reduction Technique of SDF IFFT Architecture for OFDM-Based Applications
• Memory Size Reduction Technique of SDF IFFT Architecture for OFDM-Based Applications
• Memory efficient IFFT design for OFDM-based applications

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