Low Power Small Area Modified Booth Multiplier Design for Predetermined Coefficients(VLSI Design Technology and CAD)

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概要

• 論文の詳細を見る

• In this paper, based on the variation of the modified Booth encoding method, an efficient modified Booth multiplier design method for predetermined coefficient groups is proposed. In the case of pulse-shaping filter design used in CDMA, it is shown that by the proposed method, area and power consumption can be reduced up to 44% and 48%, respectively, compared with the conventional designs. Also, it is shown that in the case of 128-point radix-2^4 FFT, the area and power consumption can be reduced by 18% and 36%, respectively.

• 社団法人電子情報通信学会の論文
• 2007-03-01

著者

• Cho Kyung‐ju

  Korea Assoc. Of Aids To Navigation (kaan) Seoul Kor

• Chung Jin‐gyun

  Chonbuk National Univ. Jeonju Kor

• KIM Yong-Eun

  Dept. of Electronics & Information Engr. at Chonbuk National University

• CHO Kyung-Ju

  Dept. of Electronics & Information Engr. at Chonbuk National University

• CHUNG Jin-Gyun

  Dept. of Electronics & Information Engr. at Chonbuk National University

• Kim Yong-eun

  Division Of Electronics & Information Engr. Chonbuk National University

関連論文

• CSD-Based Programmable Multiplier Design for Predetermined Coefficient Groups
• Low Power Small Area Modified Booth Multiplier Design for Predetermined Coefficients(VLSI Design Technology and CAD)
• Adaptive Error Compensation for Low Error Fixed-Width Squarers(Computer Components)
• Fixed-Width Group CSD Multiplier Design

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