A 3.2-GHz Down-Spread Spectrum Clock Generator Using a Nested Fractional Topology

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概要

• 論文の詳細を見る

• A high-speed triangular-modulated spread-spectrum clock generator using a fractional phase-locked loop is presented. The fractional division is implemented by a nested fractional topology, which is constructed from a dual-modulus divide-by-(N-1/16)/N divider to divide the VCO outputs as a first division period and a fractional control circuit to establish a second division period to cause the overall fractional division. The dual-modulus divider introduces a delay-locked-loop network to achieve phase compensation. Operating at the frequency of 3.2GHz, the measured peak power reduction is around 16dB for a deviation of 0.37% and a frequency modulation of 33kHz. The circuit occupies 1.4×1.4mm2 in a 0.18-μm CMOS process and consumes 52mW.

• （社）電子情報通信学会の論文
• 2008-02-01

著者

• Yang Ching-yuan

  Department Of Electrical Engineering National Chung Hsing University

• Chang Chih-hsiang

  Graduate Institute Of Electrical Engineering National Chung Hsing University

• WONG Wen-Ger

  Sonix Technology Corp.

関連論文

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• A 3.2-GHz Down-Spread Spectrum Clock Generator Using a Nested Fractional Topology
• Injection-Locked Clock Recovery Using a Multiplexed Oscillator for Half-Rate Data-Recovered Applications
• A 1V CMOS Dynamic Back-Gate Forward Bias Prescaler for Frequency Synthesizer Application
• High-Frequency Low-Noise Voltage-Controlled LC-Tank Oscillators Using a Tunable Inductor Technique(Novel Device Architectures and System Integration Technologies)

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