A 1.25-Gb/s Burst-Mode Half-Rate Clock and Data Recovery Circuit Using Realigned Oscillation(Electronic Circuits)
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概要
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In this letter, a 1.25-Gb/s 0.18-μm CMOS half-rate burst-mode clock and data recovery (CDR) circuit is presented. The CDR contains a fast-locking clock recovery circuit (CRC) using a realigned oscillation technique to recover the desired clock. To reduce the power dissipation, the CRC uses a two-stage ring structure and a current-reused concept to merge with an edge detector. The recovered clock has a peak-to-peak jitter of 34.0ps at 625MHz and the retimed data has a peak-to-peak jitter of 44.0ps at 625Mb/s. The occupied die area of the CDR is 1.4×1.4mm^2, and power consumption is 32mW under a 1.8-V supply voltage.
- 2007-01-01
著者
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Yang Ching-yuan
Department Of Electrical Engineering National Chung Hsing University
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Lin Jung-mao
Department Of Electrical Engineering National Chung Hsing University
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