アクティブインダクタの対称構成による低消費電力化

概要

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This paper proposes power-consumption and chip-area reduction technique for OTA-C based active inductors. In the proposed technique a conventional floating active inductor is divided into two identical active inductors whose chip-size and power consumption are half of the original one. The two divided active inductors are connected in parallel. In the parallel connection opposite ends of the two divided active inductors are connected. Thanks to this modification two pairs of OTAs can be merged and the total number of OTAs is minimized. The proposed technique ideally achieves 33 % reduction in power consumption and more than 33 % reduction in chip-area of the conventional active inductor. Moreover, the proposed active inductor has low mismatch characteristics because it is perfectly symmetrical. It is also shown that the proposed technique is vely effective in low power design of a pair of active inductors for fully balanced circuits.
社団法人電気学会の論文
2009-08-01