A Double-Gate device architecture optimization for sub-45nm digital CMOS technologies using cell-based timing analysis

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概要

• 論文の詳細を見る
• 2005-09-13

著者

• Van Dal

  Philips Research Leuven

• PAWLAK B.

  Philips Research Leuven

• SURDEANU R.

  Philips Research Leuven

• Ponomarev Y.

  Philips Research Leuven

• Ponomarev Y.

  Philips Research Laboratories

• DOORNBOS G.

  Philips Research Leuven

• NG R.

  Philips Research Leuven

• CHRISTIE P.

  Philips Research Leuven

• NGUYEN V.

  Philips Research Leuven

• LOO J.

  Philips Research Leuven

関連論文

• Integration of ultra shallow junctions in PVD TaN nMOS transistors with Flash Lamp Annealing
• Integrating Diffusionless Anneals Into Advanced CMOS Technologies
• A Double-Gate device architecture optimization for sub-45nm digital CMOS technologies using cell-based timing analysis
• Measurement of Hole Transport Parameters in Ultra-Thin SiGe Layers and Their Application in 2D Device Simulations of Heterojunction pMOSFETs

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