Minimizing the Number of Empty Rooms on Floorplan by Dissection Line Merge(Programmable Logic, VLSI, CAD and Layout, <Special Section>Recent Advances in Circuits and Systems-Part 1)

スポンサーリンク

概要

• 論文の詳細を見る

• This paper discusses how to minimize the number of dissection lines regarded as wiring channels on a floorplan corresponding to a placement of n modules. In a floorplan (rectangular dissection), the number of dissection lines exceeds the number of rooms exactly by three. Since a floorplan obtained from a given module placement may have many empty rooms where no module is assigned, redundant wiring channels and wire bends may also be generated. Hence, in order to reduce redundant channels and wire bends, removal of empty rooms is required. For this purpose, we formulate a problem of obtaining a floorplan with the minimum possible empty rooms based on a given module placement. Then, we propose a method of removing as many redundant empty rooms as possible by merging dissection lines on a floorplan in O(n) time. The number of empty rooms in the resultant floorplan is reduced to n-⌊√<4n-1>&rfloor or less.

• 社団法人電子情報通信学会の論文
• 2005-07-01

著者

• FUJIYOSHI Kunihiro

  Department of Electrical and Electronic Engineering, Tokyo University of Agriculture & Technology

• Kodama Chikaaki

  Department Of Electric And Electronic Engineering Tokyo University Of Agriculture & Technology

• Kodama Chikaaki

  Department Of Electronic And Information Engineering Tokyo University Of Agriculture & Technolog

• Fujiyoshi Kunihiro

  Department Of Electrical And Electronic Engineering Tokyo University Of Agriculture & Technology

• Fujiyoshi Kunihiro

  Department Of Electronic And Information Engineering Tokyo University Of Agriculture & Technolog

• FUJIYOSHI Kunihiro

  Department of Electric and Electronic Engineering, Tokyo University of Agriculture & Technology

関連論文

• An Improved Method of Convex Rectilinear Block Packing Based on Sequence-Pair(Place and Routing)(VLSI Design and CAD Algorithms)
• The O-Sequence : Representation of 3D-Dissection
• An Efficient Decoding Method of Sequence-Pair with Reduced Redundancy(Special Section on VLSI Design and CAD Algorithms)
• A Graph Based Soft Module Handling in Floorplan(Floorplan and Placement, VLSI Design and CAD Algorithms)
• Minimizing the Number of Empty Rooms on Floorplan by Dissection Line Merge(Programmable Logic, VLSI, CAD and Layout, Recent Advances in Circuits and Systems-Part 1)
• Placement with Symmetry Constraints for Analog IC Layout Design Based on Tree Representation
• On the Number of Rooms in a Rectangular Solid Dissection

スポンサーリンク