A Graph Based Soft Module Handling in Floorplan(Floorplan and Placement, <Special Section>VLSI Design and CAD Algorithms)
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概要
- 論文の詳細を見る
In the VLSI layout design, a floorplan is often obtained to define rough arrangement of modules in the early design stage. In the stage, the aspect ratio of each soft module is also determined. The aspect ratio can be changed in the designated range keeping its area of each module. In this paper, in order to determine the aspect ratio, we propose a graph-based one dimensional compaction method which determines the aspect ratio quickly under the constraint that topology of a floorplan must not be changed. The proposed method is divided into two steps : (1) Selection of a minimal set of soft modules to adjust the aspect ratio. (2) Decision on the aspect ratio. (1) is formulated as the minimal cut problem in graph theory. We solve the problem by transforming it to the shortest path problem. (2) is divided into two operations. One is to determine the increment limit in height or width of each soft module and the other is to determine the aspect ratio of each soft module by Newton-Raphson method. The experimental comparisons show effectiveness of the proposed method.
- 社団法人電子情報通信学会の論文
- 2005-12-01
著者
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FUJIYOSHI Kunihiro
Department of Electrical and Electronic Engineering, Tokyo University of Agriculture & Technology
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Kodama Chikaaki
Department Of Electric And Electronic Engineering Tokyo University Of Agriculture & Technology
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ITOGA Hiroaki
Department of Electric and Electronic Engineering, Tokyo University of Agriculture & Technology
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Itoga Hiroaki
Department Of Electric And Electronic Engineering Tokyo University Of Agriculture & Technology:(
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Fujiyoshi Kunihiro
Tokyo Univ. Agriculture And Technol. Koganei‐shi Jpn
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Fujiyoshi Kunihiro
Department Of Electrical And Electronic Engineering Tokyo University Of Agriculture & Technology
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FUJIYOSHI Kunihiro
Department of Electric and Electronic Engineering, Tokyo University of Agriculture & Technology
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- A Graph Based Soft Module Handling in Floorplan(Floorplan and Placement, VLSI Design and CAD Algorithms)
- Minimizing the Number of Empty Rooms on Floorplan by Dissection Line Merge(Programmable Logic, VLSI, CAD and Layout, Recent Advances in Circuits and Systems-Part 1)
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