Placement with Symmetry Constraints for Analog IC Layout Design Based on Tree Representation
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概要
- 論文の詳細を見る
Symmetry constrains are the constraints that the given cells should be placed symmetrically in design of analog ICs. We use O-tree to represent placements and propose a decoding algorithm which can obtain one of the minimum placements satisfying the constraints. The decoding algorithm uses linear programming, which is too much time consuming. Therefore we propose a graph based method to recognize if there exists no placement satisfying both the given symmetry and O-tree constraints, and use the method before application of linear programming. The effectiveness of the proposed method was shown by computational experiments.
- (社)電子情報通信学会の論文
- 2009-02-01
著者
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Fujiyoshi Kunihiro
Department Of Electrical And Electronic Engineering Tokyo University Of Agriculture And Technology
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Fujiyoshi Kunihiro
Department Of Electrical And Electronic Engineering Tokyo University Of Agriculture & Technology
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HIRAKAWA Natsumi
Department of Electrical and Electronic Engineering, Tokyo University of Agriculture and Technology
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Hirakawa Natsumi
Department Of Electrical And Electronic Engineering Tokyo University Of Agriculture And Technology
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FUJIYOSHI Kunihiro
Department of Electric and Electronic Engineering, Tokyo University of Agriculture & Technology
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- A Graph Based Soft Module Handling in Floorplan(Floorplan and Placement, VLSI Design and CAD Algorithms)
- Minimizing the Number of Empty Rooms on Floorplan by Dissection Line Merge(Programmable Logic, VLSI, CAD and Layout, Recent Advances in Circuits and Systems-Part 1)
- Placement with Symmetry Constraints for Analog IC Layout Design Based on Tree Representation
- On the Number of Rooms in a Rectangular Solid Dissection