Atomistic Approach for Nanoscale Devices at the Scaling Limit and Beyond-Valley Splitting in Si
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概要
- 論文の詳細を見る
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2005-04-30
著者
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RAHMAN Anisur
School of ECE, Network for Computational Nanotechnology Purdue University
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KLIMECK Gerhard
School of ECE, Network for Computational Nanotechnology Purdue University
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VAGIDOV Nizami
Department of EE, State University of New York
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BOYKIN Timothy
Department of Elec. and Comp. Engineering, University of Alabama
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LUNDSTROM Mark
School of ECE, Network for Computational Nanotechnology Purdue University
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Rahman Anisur
School Of Electrical And Computer Engineering Network For Computational Nanotechnology Purdue Univer
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Rahman Anisur
School Of Ece Network For Computational Nanotechnology Purdue University
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Lundstrom Mark
School Of Ece Network For Computational Nanotechnology Purdue University
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Vagidov Nizami
Department Of Ee State University Of New York
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Boykin Timothy
Department Of Elec. And Comp. Engineering University Of Alabama
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Klimeck Gerhard
School Of Ece Network For Computational Nanotechnology Purdue University
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Lundstrom Mark
School of Electrical and Computer Engineering, Network for Computational Nanotechnology Purdue University, West Lafayette, IN 47907, USA
関連論文
- Nanoscale Device Simulation at the Scaling Limit and Beyond
- Atomistic Approach for Nanoscale Devices at the Scaling Limit and Beyond-Valley Splitting in Si
- Device Physics of Sub-100nm Transistors
- Asymmetrically Doped GaAs/AlGaAs Double-Quantum-Well Structure for Voltage-Tunable Infrared Detection
- Atomistic Approach for Nanoscale Devices at the Scaling Limit and Beyond— Valley Splitting in Si