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Univ. Kitakyushu Kitakyushu‐shi Jpn | 論文
- FPGA-Based Reconfigurable Adaptive FEC(System Level Design)(VLSI Design and CAD Algorithms)
- Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures
- Fast Scheduling and Allocation Algorithms for Entropy CODEC (Special Issue on Synthesis and Verification of Hardware Design)
- A Performance-Oriented Simultaneous Placement and Global Routing Algorithm for Transport-Processing FPGAs (Special Section on VLSI Design and CAD Algorithms)
- A Circuit Partitioning Algorithm with Path Delay Constraints for Multi-FPGA Systems (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
- Simultaneous Placement and Global Routing for Transport-Processing FPGA Layout (Special Section on VLSI Design and CAD Algorithms)
- A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for FPGAs with Path Delay Constraints (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
- A Circuit Partitioning Algorithm with Replication Capability for Multi-FPGA Systems
- Maple : A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for Field-Programmable Gate Arrays (Special Section on VLSI Design and CAD Algorithms)
- Selective Low-Care Coding : A Means for Test Data Compression in Circuits with Multiple Scan Chains(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier (System LSIs and Microprocessors, VLSI Design Technology in the Sub-100nm Era)
- A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition(Programmable Logic, VLSI, CAD and Layout, Recent Advances in Circuits and Systems-Part 1)
- Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis(Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
- High-Level Power Optimization Based on Thread Partitioning(System Level Design)(VLSI Design and CAD Algorithms)
- A Hardware/Software Cosynthesis Algorithm for Processors with Heterogeneous Datapaths(Selected Papers from the 16th Workshop on Circuits and Systems in Karuizawa)
- A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions(Design Methodology)(VLSI Design and CAD Algorithms)
- A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions(Simulation Acceletor)(VLSI Design and CAD Algorithms)
- A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions
- A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories
- A High-Level Energy-Optimizing Algorithm for System VLSIs Based on Area/Time/Power Estimation(Special Section on VLSI Design and CAD Algorithms)