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Univ. Kitakyushu Kitakyushu‐shi Jpn | 論文
- An Algorithm and a Flexible Architecture for Fast Block-Matching Motion Estimation(Special Section on VLSI Design and CAD Algorithms)
- C-5 A Software/Hardware Codesign for MPEG Encoder
- High-Level Area/Delay/Power Estimation for Low Power System VLSIs with Gated Clocks(Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa)
- A New Hardware/Software Partitioning Algorithm for DSP Processor Cores with Two Types of Register Files(Special Section on VLSI Design and CAD Algorithms)
- Area and Delay Estimation in Hardware/Software Cosynthesis for Digital Signal Processor Cores(Special Section on VLSI Design and CAD Algorithms)
- An Area/Time Optimizing Algorithm in High-Level Synthesis of Control-Based Hardwares (Special Section on Discrete Mathematics and Its Applications)
- CAM Processor Synthesis Based on Behavioral Descriptions (Special Section on VLSI Design and CAD Algorithms)
- A Hardware / Software Cosynthesis System for Digital Signal Processor Cores with Two Types of Register Files (Special Section of Selected Papers from the 12th Workshop on Circuit and Systems in Karuizawa)
- Performance Study and Deployment Strategies on the Sender-Initiated Multicast(Internet Technology V)
- Multi-Path Transmission Algorithm for End-to-End Seamless Handover across Heterogeneous Wireless Access Networks(Mobile Networking)(Internet Technology IV)
- Proposal for Adaptive Bandwidth Allocation Using One-Way Feedback Control for MPLS Networks(Switching for Communications)
- End-to-end seamless handover using Multi-path transmission algorithm (インターネットコンファレンス2003論文集)
- A Two-Level Cache Design Space Exploration System for Embedded Applications
- An L1 Cache Design Space Exploration System for Embedded Applications
- JPEG Compatible Raw Image Coding Based on Polynomial Tone Mapping Model
- Thermal-Aware Placement Based on FM Partition Scheme and Force-Directed Heuristic(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- A Scan-Based Attack Based on Discriminators for AES Cryptosystems
- X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction
- Unified Dual-Radix Architecture for Scalable Montgomery Multiplications in GF(P) and GF(2^n)
- A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss