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System Lsi Development Center Mitsubishi Electric Corporation | 論文
- Area Optimization in 6T and 8T SRAM Cells Considering V_ Variation in Future Processes(Next-Generation Memory for SoC,VLSI Technology toward Frontiers of New Market)
- Shared Multibuffer ATM Switches with Hierarchical Queueing and Multicast Functions
- A 1.5-V 250-MHz to 3.0-V 622-MHz Operation CMOS Phase-Locked Loop with Precharge Type Phase-Frequency Detector
- A Shared Multibuffer Architecture for High-Speed ATM Switch LSIs (Special Issue on New Architecture LSIs)
- An Energy-Harvesting Wireless-Interface SoC for Short-Range Data Communication
- Synthesis of Cyclic Oligomer Having a Low Ionization Potential
- A Cyclic Carbazole Oligomer for Electroluminescence Applications
- Phases and Third-Order Optical Nonlinearities in Tetravalent Metallophthalocyanine Thin Films
- Third-Order Nonlinear Optical Properties in Soluble Phthalocyanines with Tert-Butyl Substituents
- Enhancement of Third-Order Optical Nonlinearities of Soluble Vanadyl Phthalocyanines in Doped Polymer Films
- Third-Order Optical Nonlinearities in Porphyrins with Extended π-Electron Systems
- A 58-μW Single-Chip Sensor Node Processor with Communication Centric Design
- A 433-MHz Rail-to-Rail Voltage Amplifier with Carrier Sensing Function for Wireless Sensor Networks
- Counter-Based Broadcasting with Hop Count Aware Random Assessment Delay Extension for Wireless Sensor Networks
- A Sub 100mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer
- Data Transmission Scheduling Based on RTS/CTS Exchange for Periodic Data Gathering Sensor Networks(Ubiquitous Sensor Networks)
- Aggregation Efficiency-Aware Greedy Incremental Tree Routing for Wireless Sensor Networks(Mobile Multimedia Communications)
- A Method for Estimating the Mean-Squared Error of Distributed Arithmetic
- Main-Chain Polymers with Nonlinear Optical Chromophores as a Slipped Shoulder-to-Shoulder Arrangement
- A Highly Parallel DSP Architecture for Image Recognition